Semiconductor devices operate best where the power supply voltages are very stable, with few if any transients. In a typical system for semiconductor devices, Vss and Vdd are supplied using a well regulated and stable power supply. These levels are important as the absolute levels of each affect many aspects of the operation of various active devices in a semiconductor circuit. For example, the precharge of a transistor in a memory circuit depends on the levels of each of Vss and Vdd. In addition, the difference between Vss and Vdd impacts the speed of a device. Transient variations in the power levels can dynamically change the delay through circuit elements. For logic circuits, this can slow down operation of the circuit, decreasing the frequency of operation. In a phase locked loop (PLL), these power level transients are a primary source of jitter.
Despite the efforts of designers to limit transients in the power supply to individual integrated circuits (ICs) in a system, it is nearly impossible to preclude all such transients. Transients or noise may arise from other sources such as cross talk between different levels or signals. It is common to include a capacitor between Vdd and Vss or between Vdd and ground in the region of an IC to provide some amount of transient filtering. This will suppress spikes and reduce sensitivity to noise.
This is particularly common in memory modules, where a capacitor may be wired to each IC, or to a small number of equivalent ICs. A typical SIMM (single in-line memory module) or DIMM (dual in-line memory module) will have several small capacitors wired onto a printed circuit (PC) board for this purpose. Referring to FIG. 1, in a representative memory module with PC board 10, memory chips 12 are connected by traces (not shown) to edge connector fingers 13. These traces supply Vss, Vdd, ground, address, data and control signals to each IC such as memory chip 12. A bypass capacitor 11 is connected by traces 14 to Vss and Vdd of a corresponding memory chip 12.
It is advantageous to position the bypass capacitor as close to the corresponding IC device as possible. A long trace between an IC and a bypass capacitor has inherent inductance and resistance, and the effect of this parasitic inductance and resistance is more pronounced at higher frequencies. To improve the filtering, a lower trace length or larger capacitance can be designed into a circuit. For a given capacitor, the effective noise suppression is approximately inversely related to the trace length. For example, if the trace length between the capacitor and the IC can be reduced by a third, the capacitor will be approximately three times more effective in reducing noise. Thus, by positioning a capacitor closer to an IC (e.g. a memory IC), a smaller inductance is achieved, which means that a smaller capacitor can be used to achieve the same amount of filtering as a larger capacitor positioned farther away (and thus having a higher inductance).
Typical memory chips are packaged in a variety of materials, generally plastic or ceramic, with leads extending outside the package. The present trend in packaging for higher interconnect density is towards Ball Grid Array (BGA) packages, where the PC board connections are closely spaced in a grid underneath the middle of the chip's package. These leads are soldered to corresponding terminals on the printed circuit board of a module or motherboard, with the package essentially flush with the PC board. The designer will position a bypass capacitor as close as convenient, but restrictions include the proximity of other devices such as other ICs, and the location and routing of other traces. In a multilayer board, quite common in modern designs, the connection to the bypass capacitor will be at least millimeters and often centimeters in length.
Recent advances in chip packaging now permit a semiconductor die to be positioned a short distance away from the corresponding PC board, module, or other connection device. In particular, the use of small spring structures such as MicroSpring.TM. contact structures using FormFactor technology, positions the IC on the order of 20 mils (500 microns or 0.5 mm) above the PC board. Construction of suitable devices is described in detail in U.S. patent application Ser. No. 08/340,144, filed Nov. 15, 1994, entitled "Contact Structure for Interconnections, Interposer, Semiconductor Assembly", inventors Igor Y. Khandros and Gaetan L. Mathieu, (hereinafter the "Parent" case). That application is incorporated herein by reference in its entirety. The corresponding PCT application was published May 26, 1995 as WO 95/14314.
In the Parent case, FIG. 32 illustrates a capacitor positioned between a semiconductor device and a support PC board. An alternative description of making spring members can be found in U.S. patent application Ser. No. 08/526,246, filed Sep. 21, 1995, entitled "Composite Interconnection Elements for Microelectronic Components and Methods of Making Same", commonly assigned with the present application. The corresponding PCT application was published May 30, 1996 as WO 96/16440. These disclosures detail bonding a flexible material to an electronic component such as a semiconductor device, forming it into a springable shape, then coating it with a hard material to form a resilient, free-standing electrical contact structure. Such resilient contacts preferably extend some 20 to 40 mils from the surface of a semiconductor wafer. The resilient contact can be connected to terminals on a second electronic component such as a PC board in a variety of ways, such as by soldering.
Referring to FIG. 2, memory chip 12 includes terminals 23 which are often bonding pads on a passivated surface of the IC. For many of the terminals 23, a resilient contact 21 is bonded to the terminal as described in the parent application and in the '246 application. Each resilient contact has a free end that is positioned to mate with a corresponding terminal 22 on PC board 10. The resilient contact may be connected to the terminal 22 by soldering, brazing, conductive epoxy and the like (not shown). Alternatively, the resilient contact may be brought into pressure contact with the corresponding terminal, then secured in place reversibly, as in a socket or clamp, or secured permanently, as with potting compound, which may fully engulf and surround the memory chip 12.
Two terminals 23A are provided to connect bypass capacitor 11 by means of capacitor contacts 11A. In FIG. 32 of the Parent application a similar structure is shown with the capacitor connected to the PC board, not the semiconductor. The resilient contact elements are shown connected to the semiconductor device but could have been secured to the PC board or other suitable substrate and then later connected to the semiconductor device. Each of these general embodiments are useful. Where the capacitor can fit between the semiconductor device and the corresponding mating component, such as a PC board, contact elements can be secured to the semiconductor device or the mating component, or even to each. It will be appreciated that chip 12 may be some type of IC other than a memory chip.
Referring to FIG. 3, FIG. 2 is seen to be a cross-section slice taken along line 2--2. FIG. 3 is a cross section, plan view of semiconductor device 12 over PC board 10, with the contact elements (terminals 23) on the bottom of semiconductor device 12 shown in solid lines for clarity. See line 3--3 in FIG. 2. In this embodiment, terminals 22 on PC board 10 are shown to be offset in X and Y from terminals 23 according to the shape of resilient contacts 21. However the particular offset of the terminals and the shape and dimensions of a contact terminal may be selected in coordination according a number of design criteria by one skilled in the art. For example, balls are generally spherical, so corresponding terminals would be positioned in very close proximity. However, using the shapeable resilient contact elements described above, the vector between base and contact region can be varied significantly, allowing for considerable flexibility in the relative placement of terminals on the semiconductor and mating component.
The position where a terminal is laid out on a semiconductor is selected according to various design criteria. A typical semiconductor device is designed for the intended final packaging. The traditional structure is a peripheral array, with contact terminals arranged along or near the periphery of the active circuitry. Another traditional structure is lead-on-center or LOC, where the terminals are along a line approximately bisecting the active circuitry. Some devices are prepared for connection as an area array, generally regularly spaced over much of the area of the active circuit. Concentration of terminals in a region of the chip allows for the association of specialized circuitry for interfacing through terminals, such as buffering, I/O control, and ESD protection.
The position of the base of a resilient contact element on a semiconductor device can be varied with significant freedom. Referring to co-pending, commonly assigned priority application Ser. No. 08/955,001, filed Oct. 20, 1997, entitled "Electronic Component With Terminals And Spring Contact Elements Extending From Areas Which Are Remote From The Terminals," a product is described for creating a resilient contact base at some distance from the original semiconductor terminal, and creating a resilient contact at that remote location. That application is incorporated herein by reference in its entirety. Of course, a resilient contact can be fabricated just at the terminal as well.
A device designed with a primary terminal layout pattern can be remapped to a second terminal layout pattern, preferably using the method described in that application Ser. No. 08/955,001 disclosure. Depending on the design of the contact structures, a third layout pattern may pertain to the contact region of the contact structures. In one preferred example, a peripheral pad array, or a LOC array, can be modified to an area array. Among other advantages, this generally provides for a greater pitch between contact elements as compared with the original pad layout. It is preferred that the area array pitch is compatible with PC board design rules. Thus, using the resilient contact structures of the invention, a semiconductor device can be connected directly to a PC board.
Before the present invention, there was no way to position a capacitor or other electrical element directly between a semiconductor device and a second electronic component, in the context of chip scale packaging. Because the capacitor could be positioned only nearby, the necessary trace length required that larger capacitors be specified, thus preventing any attempts to position the capacitor directly at the semiconductor--component interface.
These same limitations pertain to the incorporation of other electronic components in the immediate proximity of a semiconductor device. Circuits frequently call for the inclusion of a pull-up or pull-down resistor. Such devices often are provided in a substrate such as a PC board nearby the active device, but the position of such a resistor will impact signal fidelity on the relevant signals. Placing such a resistor in the immediate proximity of a semiconductor would provide significant advantages. Other circuit elements also could be connected very close to a semiconductor device if the circuit element is sufficiently small and the semiconductor device is packaged to provide sufficient room for this connection.